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? semiconductor components industries, llc, 2013 november, 2013 ? rev. 1 1 publication order number: ncp1615/d ncp1615 high voltage high efficiency power factor correction controller the ncp1615 is a high voltage pfc controller designed to drive pfc boost stages based on an innovative current controlled frequency foldback (ccff) method. in this mode, the circuit operates in critical conduction mode (crm) when the inductor current exceeds a programmable value. when the current is below this preset level, the ncp1615 linearly decays the frequency down to a minimum of about 26 khz at the sinusoidal zero ? crossing. ccff maximizes the efficiency at both nominal and light load. in particular, the standby losses are reduced to a minimum. innovative circuitry allows near ? unity power factor even when the switching frequency is reduced. the integrated high voltage start ? up circuit eliminates the need for external start ? up components and consumes negligible power during normal operation. housed in a soic ? 14 or soic ? 16 package, the ncp1615 incorporates the features necessary for robust and compact pfc stages, with few external components. general features ? high voltage start ? up circuit with integrated brownout detection ? input to force controller into standby mode ? restart pin allows adjustment of bulk voltage hysteresis in standby mode ? skip mode near the line zero crossing ? fast line / load transient compensation ? valley switching for improved efficiency ? high drive capability: ? 500 ma/+800 ma ? wide v cc range: from 9.5 v to 28 v ? input voltage range detection ? input x2 capacitor discharge circuitry ? power saving mode (psm) enables < 30 mw no ? load power consumption ? this is a pb and halogen free device safety features ? adjustable bulk undervoltage detection (buv) ? soft overvoltage protection ? line overvoltage protection ? overcurrent protection ? open pin protection for fb and fovp/buv pins ? internal thermal shutdown ? bi ? level latch input for ovp and otp ? bypass/boost diode short circuit protection ? open ground pin protection typical applications ? pc power supplies ? off line appliances requiring power factor correction ? led drivers ? flat tvs pin connections hvfb fb restart fovp/buv vcontrol ffcontrol fault stdby hv vcc drv gnd cs/zcd pfcok pstimer ncp1615 16 pins (top view) ncp1615 14 pins (top view) fb restart fovp/buv vcontrol ffcontrol fault stdby hv vcc drv gnd cs/zcd pfcok soic ? 14 nb case 751an marking diagrams http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ordering information 1 14 ncp1615xg awlyww 1 14 ncp1615x = specific device code x = a, b, c or d a = assembly location wl = wafer lot y = year ww = work week g = pb ? free package soic ? 16 nb case 752ac 1 16 1 16 ncp1615xg awlyww
ncp1615 http://onsemi.com 2 figure 1. ncp1615c/d typical application circuit figure 2. ncp1615a/b typical application circuit n1 l n dhv2 rhv2 l1 dhv1 rhv1 drv rrestart2 rrestart1 cvcc ccomp2 cbulk bd1 bd2 bd3 bd4 daux dbypass dboost rfb2 lcm lboost mboost lin f1 rfb1 cx1 rfovp/buv2 rfovp/buv1 rff rcomp1 rzcd rcs rgs rsense raux rdrv ccomp1 cin1 cin2 drv standby pfcok l1 n1 rv1 rfault u1 ncp1615a/b control ffcontrol cs/zcd stdby vcc restart hv fb fovp/buv drv pfcok gnd fault rx1 rx2 vaux ext. vcc vaux rpsm n1 cpsm l n dhv2 rhv2 l1 dhv1 rhv1 drv psm_control rrestart2 rrestart1 cvcc ccomp2 cbulk bd1 bd2 bd3 bd4 daux dbypass dboost rfb2 lcm lboost mboost lin f1 rfb1 cx1 rfovp/buv2 rfovp/buv1 rff rcomp1 rzcd rcs rgs rsense raux rdrv ccomp1 cin1 cin2 drv standby pfcok l1 n1 rv1 u1 ncp1615c/d control ffcontrol pstimer cs/zcd stdby vcc restart hv fb fovp/buv drv pfcok gnd hvfb fault rfault vaux ext. vcc vaux
ncp1615 http://onsemi.com 3 figure 3. ncp1615 functional block diagram error amplifier pfc_ok control fb staticovp r s q clk gnd clamp drv regulator vref iref vdd cs/zcd current limit comparator zcd comparator detection of excessive current drv ocp overstress zcd current information generator and dead ? time control ffcontrol dt clk overstress drv zcd llline pfcok drv drv ? + stdby standby leb leb central logic thermal shutdown restart line removal detector brownout detector line sense detector lline line removal bo_nok hv fb logic softovp uvp1 dre in_regulation dre level shift vton processing circuitry dt skip softovp internal timing ramp lline drv pwm comparator restart_ok standby lower clamp upper clamp off bo off bo stop pwm r s q in_regulation pfc_ok clear pfcok driver skip ocp staticovp stop overstress line_ovp pwm standby vton off vton off pfc_ok clear pfc_ok stdwn uvp1 enable pfc line ovp blank delay line_ovp fovp/ restart_ok + ? blanking delay ovp comparator ? + + ? otp comparator ? + fault blanking delay delay auto ? recovery control auto ? recovery enable pfc auto ? recovery latch latch version c/d version a/b version b/d version a/c enable pfc fbhv power saving mode (psm) detector in psm in psm pstimer in psm in psm istart1 istart2 buv vcc v regul v dd i fault v regul i sense i cc(discharge) v cc(reset) v cc(on) /v cc(off) v fovp v buv i sense v uvp2 v uvp3 v restart i fovp/uvp(bias) i restart(bias) v cc v standby v dd v dd v ocp v zcd(rising) / v zcd(falling) t ovs(leb) t ocp(leb) t off1 v dd v dd v ps_in / v ps_out v pstimer2 i cs/zcd2 i cs/zcd1 i pstimer2 i pstimer1 v dd v dd r fault(clamp) v fault(clamp) v fault(otp) t delay(ovp) v fault(ovp) t delay(otp) t blank(otp) i control(bo) i fb(bias) v ref i boost(dre) i boost(startup) v dd
ncp1615 http://onsemi.com 4 table 1. pin function description pin number name function ncp1615c/d ncp1615a/b 1 n/a fbhv high voltage pfc feedback input. an external resistor divider is used to sense the pfc bulk voltage. the divider high side resistor chain from the pfc bulk voltage connects to this pin. an internal high ? voltage switch disconnects the high side resistor chain from the low side resistor when the pfc is latched or in psm in order to reduce input power. 2 1 fb this pin receives a portion of the pfc output voltage for the regulation and the dynamic response enhancer (dre) that speeds up the loop response when the output voltage drops below 95.5% of the regulation level. v fb is also the input signal for the soft ? overvoltage comparators as well as the undervoltage (uvp) comparator. the uvp comparator prevents operation as long as v fb is lower than 12% of the reference voltage (v ref ). the soft ? overvoltage comparator (soft ? ovp) gradually reduces the duty ratio to zero when v fb exceeds 105% of v ref . a 250 na sink current is built ? in to trigger the uvp protection and disable the part if the feedback pin is accidentally open. a dedicated comparator monitors the bulk voltage and disables the controller if a line overvoltage fault is detected. 3 2 restart this pin receives a portion of the pfc output voltage for determining the restart level after entering standby mode. 4 3 fovp/buv input terminal for the fast overvoltage (fast ? ovp) and bulk undervoltage (buv) comparators. the circuit disables the driver if the v fovp/buv exceeds the v fovp threshold which is set 2% higher than the reference for the soft ? ovp comparator monitoring the fb pin. this allows the both pins to receive the same portion of the output voltage. the buv comparator trips when v fovp/buv falls below 76% of the reference voltage. a buv fault disables the driver and grounds the pfcok pin. the buv function has no action whenever the pfcok pin is in low state. once the downstream converter is enabled the buv comparator monitors the output voltage to ensure it is high enough for proper operation of the downstream con- verter. a 250 na current pulls down the pin and disable the controller if the pin is accidentally open. 5 4 control the error amplifier output is available on this pin. the network connected between this pin and ground sets the regulation loop bandwidth. it is typically set below 20 hz to achieve high power factor ratios. this pin is grounded when the controller is disabled. the voltage on this pin gradually increases during power up to achieve a soft ? start. 6 5 ffcontrol this pin sources a current representative to the line current. connect a resistor between this pin and gnd to generate a voltage representative of the line current. when this voltage exceeds the internal 2.5 v reference, the circuit operates in critical conduction mode. if the pin voltage is below 2.5 v, a dead ? time is gen- erated that approximately equates [83 s ? (1 ? (v ffcontrol /v ref ))]. by this means, the circuit increases the deadtime when the current is smaller and decreases the deadtime as the current increases. the circuit skips cycles whenever v ffcontrol is below 0.65 v to prevent the pfc stage from operating near the line zero crossing where the power transfer is par- ticularly inefficient. this does result in a slightly increased distortion of the current. if superior power factor is required, offset the voltage on this pin by more than 0.75 v to inhibit skip operation. 7 6 fault the controller enters fault mode if the voltage of this pin is pulled above or below the fault thresholds. a precise pull up current source allows direct interface with an ntc thermistor. fault detection triggers a latch or auto ? recovery depending on device version. 8 7 stdby this pin is used to force the controller into standby mode. 9 n/a pstimer power saving mode (psm) timer adjust. a capacitor between this pin and gnd, c pstimer , sets the delay time before the controller enters power saving mode. once the controller enters power saving mode the ic is disabled and the current consumption is reduced to a maximum of 100 a. the input filter capacitor dis- charge function is available while in power saving mode. the device enters psm if the voltage on this pin exceeds the psm threshold, v ps_in . a secondary side con- troller optocoupler pulls down on the pin to prevent the controller from entering psm when the load is connected to the power supply. the controller is enabled once v pstimer drops below v ps_out . 10 8 pfcok this pin is grounded until the pfc output has reached its nominal level. it is also grounded if the controller detects a fault. the voltage on this pin is 5 v once the controller reaches regulation.
ncp1615 http://onsemi.com 5 table 1. pin function description pin number function name ncp1615c/d function name ncp1615a/b 11 9 cs/zcd this pin monitors the mosfet current to limit its maximum current. this pin is also connected to an internal comparator for zero current detection (zcd). this comparator is designed to monitor a signal from an auxiliary winding and to detect the core reset when this voltage drops to zero. the auxiliary winding voltage is to be applied through a diode to avoid altering the current sense information for the on time (see application schematic). 12 10 gnd ground reference. 13 11 drv mosfet driver. the high current capability of the totem pole gate drive ( ? 0.5/ +0.8 a) makes it suitable to effectively drive high gate charge power mosfets. 14 12 vcc supply input. this pin is the positive supply of the ic. the circuit starts to operate when v cc exceeds v cc(on) . after start ? up, the operating range is 9.5 v up to 28 v. 15 13 removed for creepage distance. 16 14 hv this pin is the input for the line removal detection, line level detection, and brownout detection circuits. for versions c and d, this pin is also the input for the high voltage start ? up circuit. table 2. ordering information part number device marking v cc hv start ? up otp fault psm x2 discharge brownout package shipping ? ncp1615adr2g ncp1615a 10.5 v no latch no no 100 vdc soic ? 14 nb, less pin 13 (pb ? free) 3000 / tape & reel NCP1615BDR2G ncp1615b 10.5 v no auto ? recovery no no 100 vdc ncp1615cdr2g ncp1615c 17 v yes latch yes yes 100 vdc soic ? 16 nb, less pin 15 (pb ? free) 3000 / tape & reel ncp1615c2dr2g ncp1615c2 17 v yes latch yes yes 87 vdc ncp1615ddr2g ncp1615d 17 v yes auto ? recovery yes yes 100 vdc ncp1615d2dr2g ncp1615d2 17 v yes auto ? recovery yes yes 87 vdc ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp1615 http://onsemi.com 6 table 3. maximum ratings (notes 3 and 4) rating pin symbol value unit high voltage start ? up circuit input voltage hv v hv ? 0.3 to 700 v high voltage feedback input voltage fbhv v fbhv ? 0.3 to 700 v high voltage feedback input current fbhv i fbhv 0.5 ma zero current detection and current sense input voltage (note 5) cs/zcd v cs/zcd ? 0.3 to v cs/zcd(max) v zero current detection and current sense input current cs/zcd i cs/zcd +5 ma control input voltage (note 6) control v control ? 0.3 to v control(max) v supply input voltage vcc v cc(max) ? 0.3 to 28 v fault input voltage fault v fault ? 0.3 to (v cc + 0.6) v pstimer input voltage pstimer v pstimer ? 0.3 to (v cc + 0.6) v driver maximum voltage (note 7) drv v drv ? 0.3 to v drv v driver maximum current drv i drv(src) i drv(snk) 500 800 ma maximum input voltage (note 8) other pins v max ? 0.3 to 7 v maximum operating junction temperature t j ? 40 to 150 c storage temperature range t stg ?60 to 150 c lead temperature (soldering, 10 s) t l(max) 300 c moisture sensitivity level msl 1 ? power dissipation (t a = 70 c, 1 oz cu, 0.155 sq inch printed circuit copper clad) plastic package soic ? 14nb/soic ? 16nb p d 465 mw thermal resistance, junction to ambient 1 oz cu printed circuit copper clad) plastic package soic ? 14nb/soic ? 16nb r ja r jc 172 68 c/w esd capability (note 9) human body model per jedec standard jesd22 ? a114e. machine model per jedec standard jesd22 ? a114e. charge device model per jedec standard jesd22 ? c101e. > 2000 > 200 > 500 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. all references to version c include versions c/c2, unless otherwise noted. 2. all references to version d include versions d/d2, unless otherwise noted. 3. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78. 4. low conductivity board. as mounted on 80 x 100 x 1.5 mm fr4 substrate with a single layer of 50 mm 2 of 2 oz copper traces and heat spreading area. as specified for a jedec51 ? 1 conductivity test pcb. test conditions were under natural convection of zero air flow. 5. v cs/zcd(max) is the cs/zcd pin positive clamp voltage. 6. v control(max) is the control pin positive clamp voltage. 7. when v cc exceeds the driver clamp voltage (v drv(high) ), v drv is equal to v drv(high) . otherwise, v drv is equal to v cc . 8. when the voltage applied to these pins exceeds 5.5 v, they sink a current about equal to (v pin ? 5.5 v) / (4 k ). an applied voltage of 7 v generates a sink current of approximately 0.375 ma. 9. pins hv, pfbhv are rated to the maximum voltage of the part, or 700 v.
ncp1615 http://onsemi.com 7 table 4. electrical characteristics (v cc = 15 v, v hv = 120 v, v fb = 2.4 v, r hvfb = 200 k , v hvfb = 20 v, c vcontrol = 10 nf, v ffcontrol = 2.6 v, v zcd/cs = 0 v, r zcd/cs = 3 k , v fovpbuv = 2.4 v, v stdby = 1 v, v restart = 1 v, v pstimer = 0 v, v fault = open, v pfcok = open, c drv = 1 nf, for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics conditions symbol min typ max unit start ? up and supply circuits start ? up threshold a/b version c/d version v cc increasing v cc(on) 9.75 16.0 10.50 17.0 11.25 18.0 v minimum operating voltage v cc decreasing v cc(off) 8.5 9.0 9.5 v v cc hysteresis a/b version c/d version v cc(on) ? v cc(off) v cc(hys) 1.0 7.0 1.5 8.0 ? ? v internal latch / logic reset level v cc decreasing v cc(reset) 7.3 7.8 8.3 v difference between v cc(off) and v cc(reset) v cc(off) ? v cc(reset) v cc(reset) 0.5 ? ? v regulation level in power saving mode version c/d v cc(ps_on) ? 11 ? v transition from i start1 to i start2 (c/d version) v cc increasing, i hv = 650 a v cc(inhibit) ? 0.8 ? v start ? up time (c/d version) c vcc = 0.47 f, v cc = 0 v to v cc(on) t start ? up ? ? 2.5 ms inhibit current sourced from v cc pin (c/d version) v cc = 0 v, v hv = 100 v i start1 0.375 0.5 0.87 ma start ? up current sourced from v cc pin (c/d version) v cc = v cc(on) ? 0.5 v, v hv = 100 v i start2 6.5 12 16.5 ma start ? up circuit off ? state leakage current v hv = 400 v v hv = 700 v i hv(off1) i hv(off2) ? ? ? ? 30 50 a minimum voltage for start ? up circuit start ? up (c/d version) during psm (c/d version) i start2 = 6.5 ma, v cc = v cc(on) ? 0.5 v i start2 = 6.5 ma, v cc = v cc(ps_on) ? 0.5 v v hv(min) v hv(min_psm) ? ? ? ? 38 30 v supply current in power saving mode (c/d version) latch before start ? up (a/b version) standby mode no switching operating current v cc = v cc(ps_on) v fault = 4 v v cc = v cc(on) ? 0.5 v v standby = 0 v, v restart = 3 v v fb = 2.55 v f = 50 khz, c drv = open, v control = 2.5 v, v fb = 2.45 v i cc1 i cc2 i cc2b i cc3 i cc4 i cc5 ? ? ? ? ? ? ? 0.6 0.6 ? ? 2.0 0.1 1.0 1.0 1.0 2.8 3.5 ma line removal line voltage removal detection timer t line(removal) 60 100 165 ms discharge timer duration t line(discharge) 21 32 60 ms discharge current (c/d version) v cc = v cc(off) + 200 mv v cc = v cc(discharge) + 200 mv i cc(discharge) 20 10 25 16.5 30 30 ma hv discharge level (c/d version) v hv(discharge) ? ? 40 v v cc discharge level (c/d version) v cc(discharge) 3.8 4.5 5.4 v brownout detection system start ? up threshold a/b/c/d version c2/d2 version v hv increasing v bo(start) 102 86 111 95 118 102 v system shutdown threshold a/b/c/d version c2/d2 version v hv decreasing v bo(stop) 92 78 100 87 108 94 v
ncp1615 http://onsemi.com 8 table 4. electrical characteristics (v cc = 15 v, v hv = 120 v, v fb = 2.4 v, r hvfb = 200 k , v hvfb = 20 v, c vcontrol = 10 nf, v ffcontrol = 2.6 v, v zcd/cs = 0 v, r zcd/cs = 3 k , v fovpbuv = 2.4 v, v stdby = 1 v, v restart = 1 v, v pstimer = 0 v, v fault = open, v pfcok = open, c drv = 1 nf, for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol conditions brownout detection hysteresis a/b/c/d version c2/d2 version v hv increasing v bo(hys) 7 5 11 8 ? ? v brownout detection blanking time v hv decreasing, delay from v bo(stop) to drive disable t bo(stop) 43 54 65 ms control pin sink current in brownout t bo(stop) expires i control(bo) 40 50 60 a line detection high line level detection threshold v hv increasing v lineselect(hl) 232 250 267 v low line level detection threshold v hv decreasing v lineselect(ll) 220 236 252 v line select hysteresis v hv increasing v lineselect(hys) 10 ? ? v high to low line mode selector timer v hv decreasing t line 43 54 65 ms low to high line mode selector timer v hv increasing t delay(line) 200 300 400 s line valley lockout counter after t high to low line expires n ll ? 8 ? power saving mode (c/d version) psm enable threshold v pstimer increasing v ps_in 3.325 3.500 3.675 v psm disable threshold v pstimer decreasing v ps_out 0.45 0.50 0.55 v pstimer pull up current source v pstimer = 0.9 v i pstimer1 4.5 5.9 7.3 a pstimer fast pull up current source v pstimer = 3.4 v i pstimer2 800 1000 1200 a pstimer leakage current v pstimer = 4 v i pstimer(bias) ? ? 100 na i pstimer2 enable threshold v pstimer2 0.95 1.00 1.05 v filter delay before entering psm v pstimer > v ps_in t delay(ps_in) ? 40 ? s detection delay before exiting psm and turning on start ? up circuit v pstimer < v ps_out t delay(ps_out) ? ? 100 s pstimer discharge current v pstimer = v pstimer(off) + 10 mv i pstimer(dis) 160 ? ? a pstimer discharge turn off threshold v pstimer decreasing v pstimer(off) 0.05 0.10 0.15 v pfc fb switch (c/d version) pfc off ? state leakage current v pstimer = 4 v, v hvfb = 500 v i hvfb(off) ? 0.1 3 a pfc feedback switch on resistance v hvfb = 2.75 v, i hvfb = 100 a r fbswitch(on) ? ? 10 k on ? time control pfc maximum on time v hv = 162.5 v, v control = v control(max) v hv = 162.5 v, v control = 2.5 v v hv = 325 v, v control = v control(max) t on(ll) t on(ll)2 t on(hl) 20.5 9.5 5.2 23.7 11.0 6.0 27.5 13.0 7.0 s minimum on ? time v hv = 162 v v hv = 325 v t onll(min) t onhl(min) ? ? ? ? 200 100 ns current sense current limit threshold v ilim 0.46 0.50 0.54 v leading edge blanking duration t ocp(leb) 100 200 350 ns current limit propagation delay step v cs/zcd > v ilim to drv falling edge t ocp(delay) ? 40 200 ns overstress leading edge blanking duration t ovs(leb) 50 100 170 ns
ncp1615 http://onsemi.com 9 table 4. electrical characteristics (v cc = 15 v, v hv = 120 v, v fb = 2.4 v, r hvfb = 200 k , v hvfb = 20 v, c vcontrol = 10 nf, v ffcontrol = 2.6 v, v zcd/cs = 0 v, r zcd/cs = 3 k , v fovpbuv = 2.4 v, v stdby = 1 v, v restart = 1 v, v pstimer = 0 v, v fault = open, v pfcok = open, c drv = 1 nf, for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol conditions current sense over stress detection propagation delay v cs/zcd > v zcd(rising) to drv falling edge t ovs(delay) ? 40 200 ns regulation block reference voltage t j = 25 c t j = ? 40 to 125 c v ref v ref 2.45 2.44 2.50 2.50 2.55 2.56 v error amplifier current source sink v fb = 2.4 v, v vcontrol = 2 v v fb = 2.6 v, v vcontrol = 2 v i ea(src) i ea(snk) 16 16 20 20 24 24 a open loop error amplifier transconductance v fb = v ref +/ ? 100 mv g m 180 210 245 s maximum control voltage v fb = 2 v v control(max) ? 4.5 ? v minimum control voltage v fb = 2.6 v v control(min) ? 0.5 ? v ea output control voltage range v control(max) ? v control(min) v control 3.9 4.0 4.1 v dre detect threshold v fb decreasing v dre ? 2.388 ? v dre threshold hysteresis v fb increasing v dre(hys) ? ? 25 mv ratio between the dre detect threshold and the regulation level v fb decreasing, v dre / v ref k dre 95.0 95.5 96.0 % control pin source current during start ? up (c/d version) pfcok = low, v vcontrol = 2 v i control(start ? up) 80 100 113 a ea boost current during start ? up (c/d version) i boost(start ? up) ? 80 ? a control pin source current during dre v vcontrol = 2 v i control(dre) 180 220 250 a ea boost current during dre i boost(dre) ? 200 ? a pfc gate drive rise time (10 ? 90%) v drv from 10 to 90% of v drv t drv(rise) ? 40 80 ns fall time (90 ? 10%) 90 to 10% of v drv t drv(fall) ? 20 60 ns source current capability v drv = 0 v i drv(src) ? 500 ? ma sink current capability v drv = 12 v i drv(snk) ? 800 ? ma high state voltage v cc = v cc(off) + 0.2 v, r drv = 10 k v cc = 28 v, r drv = 10 k v drv(high1) v drv(high2) 8 10 ? 12 ? 14 v low stage voltage v stdby = 0 v v drv(low) ? ? 0.25 v zero current detection zero current detection threshold v cs/zcd rising v cs/zcd falling v zcd(rising) v zcd(falling) 675 200 750 250 825 300 mv zcd and current sense ratio v zcd(rising) /v ilim k zcd/ilim 1.4 1.5 1.6 ? positive clamp voltage i cs/zcd = 0.75 ma i cs/zcd = 5 ma v cs/zcd(max1) v cs/zcd(max2) 7.1 15.4 7.4 15.8 7.8 16.1 v cs/zcd input bias current v cs/zcd = v zcd(rising) v cs/zcd = v zcd(falling) i cs/zcd(bias1) i cs/zcd(bias2) 0.5 0.5 ? ? 2.0 2.0 a zcd propagation delay measured from v cs/zcd = v zcd(falling) to drv rising t zcd ? 60 200 ns minimum detectable zcd pulse width measured from v zcd(rising) to v zcd(falling) t sync ? 110 200 ns maximum off ? time (watchdog timer) v cs/zcd > v zcd(rising) t off1 t off2 80 700 200 1000 320 1300 s
ncp1615 http://onsemi.com 10 table 4. electrical characteristics (v cc = 15 v, v hv = 120 v, v fb = 2.4 v, r hvfb = 200 k , v hvfb = 20 v, c vcontrol = 10 nf, v ffcontrol = 2.6 v, v zcd/cs = 0 v, r zcd/cs = 3 k , v fovpbuv = 2.4 v, v stdby = 1 v, v restart = 1 v, v pstimer = 0 v, v fault = open, v pfcok = open, c drv = 1 nf, for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol conditions zero current detection missing valley timeout timer measured after last zcd transition t tout 20 30 50 s pull ? up current source detects open pin fault. i cs/zcd1 ? 1 ? a source current for cs/zcd impedance testing pulls up at the end of t off1 i cs/zcd2 ? 250 ? a current controlled frequency foldback dead time v ffcntrol = 2.6 v v ffcntrol = 1.75 v v ffcntrol = 1.0 v t dt1 t dt2 t dt3 ? 4.5 11 ? 6.5 13 0 7.5 15 s ffcontrol pin current v hv = 162.5v, v control = v control(max) v hv = 325 v, v control = v control(max) i dt1 i dt2 180 92 200 103 220 114 a ffcontrol skip level v ffcntrol = increasing v ffcntrol = decreasing v skip(out) v skip(in) ? 0.55 0.75 0.65 0.85 ? v ffcontrol skip hysteresis v skip(hys) 50 ? ? mv minimum operating frequency f min ? 26 ? khz feedback over and undervoltage protection soft ? ovp to v ref ratio v fb = increasing, v sovp /v ref k sovp/vref 104 105 106 % soft ? ovp threshold v fb = increasing v sovp ? 2.625 ? v soft ? ovp hysteresis v fb = decreasing v sovp(hys) 35 50 65 mv static ovp minimum duty ratio v fb = 2.55 v, v control = open d min ? ? 0 % undervoltage to v ref ratio v fb = increasing, v uvp1 /v ref k uvp1/vref 8 12 16 % undervoltage threshold v fb = decreasing v uvp1 ? 300 ? mv undervoltage to v ref hysteresis ratio v fb = increasing v uvp1(hys) ? ? 25 mv feedback input sink current v fb = v sovp , hvfb = open v fb = v uvp1 , hvfb = open i fb(snk1) i fb(snk2) 50 50 200 200 450 450 na fast overvoltage and bulk undervoltage protection (fovp and buv) fast ovp threshold v fovp/buv increasing v fovp ? 2.675 ? v fast ovp hysteresis v fovp/buv decreasing v fovp(hys) 15 30 60 mv ratio between fast and soft ovp levels k fovp/sovp = v fovp / v sovp k fovp/sovp 101.5 102.0 102.5 % ratio between fast ovp and v ref k fovp/vref = v fovp / v ref k fovp/vref 106 107 108 % bulk undervoltage threshold v fovp/buv decreasing v buv ? 1.9 ? v undervoltage protection threshold to v ref ratio v fovp/buv decreasing, v buv /v ref k buv/vref 74 76 78 % open pin detection threshold v fovp/buv decreasing v uvp2 0.2 0.3 0.4 v open pin detection hysteresis v fovp/buv increasing v uvp2(hys) ? 10 ? mv pull ? down current source v fovp/buv = v buv v fovp/ buv = v uvp2 i fovp/buv(bias1) i fovp/buv(bias2) 50 50 200 200 450 450 na line ovp ratio between line ovp and vref v fb increasing k lovp 111 112.5 114 % line overvoltage threshold v lovp ? 2.813 ? v line overvoltage filter v fb increasing t lovp(blank) 45 55 65 s standby input standby input threshold v stdby decreasing v standby 285 300 315 mv standby input blanking duration t blank(stdby) 0.8 1 1.2 ms
ncp1615 http://onsemi.com 11 table 4. electrical characteristics (v cc = 15 v, v hv = 120 v, v fb = 2.4 v, r hvfb = 200 k , v hvfb = 20 v, c vcontrol = 10 nf, v ffcontrol = 2.6 v, v zcd/cs = 0 v, r zcd/cs = 3 k , v fovpbuv = 2.4 v, v stdby = 1 v, v restart = 1 v, v pstimer = 0 v, v fault = open, v pfcok = open, c drv = 1 nf, for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol conditions restart restart threshold ratio v restart /v ref k restart 97.5 98.0 98.5 % restart threshold v restart ? 2.45 ? v restart input pull down current v restart = v uvp3 i restart(bias) 50 200 450 na open pin detection threshold v uvp3 0.2 0.3 0.4 v open pin detection hysteresis v uvp3(hys) ? 10 ? mv fault input overvoltage protection (ovp) threshold v fault increasing v fault(ovp) 2.79 3.00 3.21 v delay before fault confirmation used for ovp detection used for otp detection v fault increasing v fault decreasing t delay(ovp) t delay(otp) 22.5 22.5 30.0 30.0 37.5 37.5 s overtemperature protection (otp) threshold v fault decreasing v fault(otp_in) 0.38 0.40 0.42 v otp exiting threshold (b/d versions) v fault increasing v fault(otp_out) 0.874 0.920 0.966 v otp blanking delay during start ? up t blank(otp) 4 5 6 ms otp pull ? up current source v fault = v fault(otp_in) + 0.2 v i fault(otp) 43 46 49 a fault input clamp voltage v fault = open v fault(clamp) 1.15 1.7 2.25 v fault input clamp series resistor r fault(clamp) 1.32 1.55 1.78 k pfcok signal pfcok output voltage i pfcok = ? 5 ma v pfcok 4.75 5.00 5.25 v pfcok low state output voltage i pfcok = 5 ma v pfcok(low) ? ? 250 mv thermal shutdown thermal shutdown temperature increasing t shdn ? 150 ? c thermal shutdown hysteresis temperature decreasing t shdn(hys) ? 50 ? c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
ncp1615 http://onsemi.com 12 detailed operating description introduction the ncp1615 is designed to optimize the ef ficiency of your pfc stage throughout the load range. in addition, it incorporates protection features for rugged operation. more generally, the ncp1615 is ideal in systems where cost effectiveness, reliability, low standby power and high efficiency are the key requirements: ? current controlled frequency foldback: the ncp1615 operates in current controlled frequency foldback (ccff). in this mode, the circuit operates in classical critical conduction mode (crm) when the inductor current exceeds a programmable value. when the current falls below this preset level, the ncp1615 linearly reduces the operating frequency down to a minimum of about 26 khz when the input current reaches zero. ccff maximizes the efficiency at both nominal and light load. in particular, standby losses are reduced to a minimum. similar to frequency clamped crm controllers, internal circuitry allows near ? unity power factor at lower output power. ? skip mode: to further optimize the efficiency, the circuit skips cycles near the line zero crossing when the current is very low. this is to avoid circuit operation when the power transfer is particularly inefficient at the cost of input current distortion. when superior power factor is required, this function can be inhibited by offsetting the ffcontrol pin by 0.75 v. ? integrated high voltage start ? up circuit (versions c and d): eliminates the need of external start ? up components. it is also used to discharge the input filter capacitors when the line is removed. ? integrated x2 capacitor discharge: reduces input power by eliminating external resistors for discharging the input filter capacitor. ? pfcok signal: the pfcok pin is used to disable/enable the downstream converter. this pin is internally grounded when a fault is detected or when the pfc output voltage is below its regulation level. ? fast line / load transient compensation (dynamic response enhancer): since pfc stages exhibit low loop bandwidth, abrupt changes in the load or input voltage (e.g. at start ? up) may cause an excessive over or undervoltage condition. this circuit limits possible deviations from the regulation level as follows: ? the soft and fast overvoltage protections accurately limit the pfc stage maximum output voltage. ? the ncp1615 dramatically speeds up the regulation loop when the output voltage falls below 95.5% of its regulation level. this function is disabled during power up to achieve a soft ? start. ? power saving mode: disables the controller and reduces the input power consumption of the system enabling very low input power applications. ? standby mode input: allows the downstream converter to inhibit the pfc drive pulses when the load is reduced. ? safety protections: the ncp1615 permanently monitors the input and output voltages, the mosfet current and the die temperature to protect the system during fault conditions making the pfc stage extremely robust and reliable. in addition to the bulk overvoltage protection, the ncp1615 include: ? maximum current limit: the circuit senses the mosfet current and turns off the power switch if the maximum current limit is exceeded. in addition, the circuit enters a low duty ? ratio operation mode when the current reaches 150% of the current limit as a result of inductor saturation or a short of the bypass/boost diode. ? undervoltage protection (uvp): this circuit turns off when it detects that the output voltage is below 12% of the voltage reference (typically). this feature protects the pfc stage if the ac line is too low or if there is a failure in the feedback network (e.g., bad connection). ? bulk undervoltage detection (buv): the circuit monitors the output voltage to detect when the pfc stage cannot regulate the bulk voltage (buv fault). when the buv fault is detected, the control pin is gradually discharged followed by the grounding of the pfcok pin, to disable the downstream converter. ? brownout detection: the circuit detects low ac line conditions and stops operation thus protecting the pfc stage from excessive stress. ? thermal shutdown: an internal thermal circuitry disables the gate drive when the junction temperature exceeds the thermal shutdown threshold. ? a latch fault input can be used to disable the controller if a fault is detected (i.e. supply overvoltage, overtemperature) ? a line overvoltage circuit monitors the bulk voltage and disables the controller if voltage exceeds the overvoltage level. ? output stage totem pole driver: the ncp1615 incorporates a 0.5 a source / 0.8 a sink gate driver to efficiently drive most medium to high power mosfets. high voltage start ? up circuit versions c and d of the ncp1615 integrate a high voltage start ? up circuit accessible by the hv pin. the start ? up circuit is rated at a maximum voltage of 700 v. a start ? up regulator consists of a constant current source that supplies current from a high voltage rail to the supply capacitor on the v cc pin (c vcc ). the start ? up circuit current (i start2 ) is typically 12 ma. i start2 is disabled if the
ncp1615 http://onsemi.com 13 v cc pin is below v cc(inhibit) . in this condition the start ? up current is reduced to i start1 , typically 0.5 ma. the internal high voltage start ? up circuit eliminates the need for external start ? up components. in addition, this regulator reduces no load power and increase the system efficiency as it uses negligible power in the normal operation mode once c vcc is charged to the start ? up threshold, v cc(on) , typically 17 v (10.5 v for versions a and b), the start ? up regulator is disabled and the controller is enabled. the start ? up regulator remains disabled until v cc falls below the lower supply threshold, v cc(off) , typically 9.0 v, is reached. once reached, the pfc controller is disabled reducing the bias current consumption of the ic. the controller is disabled once a fault is detected. the controller will restart next time v cc reaches v cc(on) or after all non ? latching faults are removed. the supply capacitor provides power to the controller during power up. the capacitor must be sized such that a v cc voltage greater than v cc(off) is maintained while the auxiliary supply voltage is building up. otherwise, v cc will collapse and the controller will turn off. the operating ic bias current, i cc5 , and gate charge load at the drive outputs must be considered to correctly size c vcc . the increase in current consumption due to external gate charge is calculated using equation 1. i cc(gatecharge) f q g (eq. 1) where f is the operating frequency and q g is the gate charge of the external mosfets. operating mode the ncp1615 pfc controller achieves power factor correction using the novel current controlled frequency foldback (ccff) topology. in ccff the circuit operates in the classical critical conduction mode (crm) when the inductor current exceeds a programmable value. once the current falls below this preset level, the frequency is linearly reduced, reaching about 26 khz when the current is zero. figure 4. ccff operation as illustrated in the top waveform in figure 4, at high load, the boost stage operates in crm. as the load decreases, the controller operates in a controlled frequency discontinuous mode. figure 5 details ccff operation. a voltage representative of the input current (?current information?) is generated. if this signal is higher than a 2.5 v internal reference (named ?dead ? time ramp threshold?), there is no deadtime and the circuit operates in crm. if the current information signal is lower than the 2.5 v threshold, deadtime is added. the deadtime is the time necessary for the internal ramp to reach 2.5 v from the current information floor. hence, the lower the current information is, the longer the deadtime. when the current information is 0.75 v, the deadtime is 15 s. to further reduce the losses, the mosfet turn on is further delayed until its drain ? source voltage is at its valley. as illustrated in figure 5, the ramp is synchronized to the drain ? source ringing. if the ramp exceeds the 2.5 v threshold while the drain ? source voltage is below v in , the ramp is extended until it oscillates above v in so that the drive will turn on at the next valley.
ncp1615 http://onsemi.com 14 figure 5. dead ? time generation current information generation the ffcontrol pin sources a current that is representative of the input current. in practice, i ffcontrol is built by multiplying the internal control signal (v regul , i.e., the internal signal that controls the on time) by the internal sense voltage (v sense ) that is proportional to the input voltage seen on the hv pin (see figure 6). the multiplier gain ( k m of figure 6) is four times less in high line conditions (that is when the ?lline? signal from the brownout block is in low state) so that i ffcontrol provides a voltage representative of the input current across resistor r ff placed between the ffcontrol pin and ground. the ffcontrol voltage, v ffcontrol , is representative of the current information. figure 6. generation of the current information in the ncp1615 + multiplier pfc_ok control ffcontrol skip i sense i regul llline v to i converter i regul = k*v regul k m *i regul *i sense ramp sum brown ? out and line range detection i sense v skip(in)/ v skip(out) hv
ncp1615 http://onsemi.com 15 skip mode as illustrated in fi gure 6 the circuit also skips cycles near the line zero crossing where the current is very low and subsequently the voltage across rff is low. a comparator monitors v ffcontrol and inhibits the switching operation when v ffcontrol falls below the skip level, v skip(in) , typically 0.65 v. switching resumes when v ffcontrol exceeds the skip exit threshold, v skip(out) , typically 0.75 v (100 mv hysteresis). this function disables the driver to reduce power dissipation when the power transfer is particularly inefficient at the expense of slightly increased input current distortion. when superior power factor is needed, this function can be inhibited offsetting the ffcontrol pin by 0.75 v. the skip mode capability is disabled whenever the pfc stage is not in nominal operation represented by the pfcok signal. the circuit does not abruptly interrupt the switching when v ffcontrol falls below v skip(in) . instead, the signal v ton that controls the on time is gradually decreased by grounding the v regul signal applied to the v ton processing block shown in figure 11. doing so, the on time smoothly decays to zero in 3 to 4 switching periods typically. figure 7 shows the practical implementation of the ffcontrol circuitry. figure 7. ccff practical implementation 200 us delay (watchdog) s r q vzcd(th) drv drv s r q drv s r q drv timeout delay clk 2.5 v zero current detection dead ? time (dt) detection ramp for dt control cs / zcd ffcontrol clock generation dt sum ccff maximizes the efficiency at both nominal and light load. in particular, the standby losses are reduced to a minimum. also, this method avoids that the system stalls or jumps between drain voltage valleys. instead, the circuit acts so that the pfc stage transitions from the n valley to (n + 1) valley or vice versa from the n valley to (n ? 1) cleanly as illustrated by figure 8. figure 8. valley transitions without valley jumping
ncp1615 http://onsemi.com 16 on time modulation let?s analyze the ac line current absorbed by the pfc boost stage. the initial inductor current at the beginning of each switching cycle is always zero. the coil current ramps up when the mosfet is on. the slope is (vin/l) where l is the coil inductance. at the end of the on time period (t 1 ), the inductor starts to demagnetize. the inductor current ramps down until it reaches zero. the duration of this phase is (t 2 ). in some cases, the system enters then the dead ? time (t 3 ) that lasts until the next clock is generated. one can show that the ac line current is given by: i in v in t 1 t 1 t 2 2tl (eq. 2) where t = (t 1 + t 2 + t 3 ) is the switching period and v in is the ac line rectified voltage. in light of this equation, we immediately note that i in is proportional to v in if [t 1 *(t 1 + t 2 )/t] is a constant. figure 9. pfc boost converter (left) and inductor current in dcm (right) the ncp1615 operates in voltage mode. as portrayed by figure 10, t 1 is controlled by the signal v ton generated by the regulation block and an internal ramp as follows: t 1 c ramp v ton i ch (eq. 3) the charge current is constant at a given input voltage (as mentioned, it is four times higher at high line compared to its value at low line). c ramp is an internal timing capacitor. the output of the regulation block, v control , is linearly transformed into the signal v regul varying between 0 and 1.5 v. v regul is the voltage that is injected into the pwm section to modulate the mosfet duty ratio. the ncp1615 includes circuitry that processes v regul to generate the v ton signal that is used in the pwm section (see figure 11). it is modulated in response to the deadtime sensed during the precedent current cycles, that is, for a proper shaping of the ac line current. this modulation leads to: v ton t v regul t 1 t 2 (eq. 4) or v ton t 1 t 2 t v regul given the low regulation bandwidth of the pfc systems, v control and thus v regul are slow varying signals. hence, the (v ton *(t 1 + t 2 )/t) term is substantially constant. provided that during t 1 it is proportional to v ton , equation 2 leads to: i in k v in , where k is a constant. k constant 1 2l v regul v regul(max) t on(max) where t on(max) is the maximum on time obtained when v regul is at its maximum level, v regul(max) . the parametric table shows that t on(max) is equal to 25 s (t on(ll) ) at low line and to 6.3 s (t on(hl) ) at high line. hence, we can rewrite the above equation as follows: i in v in t on(ll) 2 l v regul v regul(max) at low line. i in v in t on(hl) 2 l v regul v regul(max) from these equations, we can deduce the expression of the average input power at low line as shown below: p in(ave) v in,rms 2 t on(ll) v regul 2 l v regul(max) the input power at high line is shown below: p in(ave) v in,rms 2 t on(hl) v regul 2 l v regul(max) hence, the maximum power that can be delivered by the pfc stage at low line is given by equation below: p in(max) v in,rms 2 t on(ll) 2 l the maximum power at high line is given by the equation below: p in(max) v in,rms 2 t on(hl) 2 l the input current is then proportional to the input voltage resulting in a properly shaped ac line current.
ncp1615 http://onsemi.com 17 one can note that this analysis is also valid in crm operation. this condition is just a particular case of this functioning where (t 3 = 0), which leads to (t 1 + t 2 = t) and (v ton = v regul ). that is why the ncp1615 automatically adapts to the conditions and transitions from dcm to crm (and vice versa) without power factor degradation and without discontinuity in the power delivery. figure 10. pwm circuit and timing diagram pwm comparator turns off mosfet v ton ramp voltage pwm output closed when output low v ton c ramp i ch figure 11. v ton processing circuit pwm comparator to pwm latch c1 s3 s1 s2 r1 oa1 stop ocp dt (high during dead ? time) in1 internal timing saw ? tooth v ton v regul ? >v ton during (t1+t2) ? >0 v during t3 (dead ? time) ? >v ton *(t1+t2)/t in average the integrator oa1 amplifies the error between v regul and in1 so that on average, v ton *t 1 +t 2 )/t) equates v regul . it is important to note that the ?vt on processing circuit? compensates for long interruption of the driver activity by grounding the v ton signal as shown in figure 11. long driver interruptions are represented by the stop signal. such faults (excluding ocp) are buv_fault, ovp, bonok, overstress, skip, staticovp, fast ? ovp, restartnok and off mode. otherwise, a long off time will be interpreted as normal deadtime and the circuit would over dimension v ton to compensate it. grounding the v ton signal leads to a short soft ? start period due to ramp up of v ton . this helps reduce the risk of acoustic noise. voltage reference a transconductance error amplifier regulates the pfc output voltage, v bulk , by comparing the pfc feedback signal to an internal reference voltage, v ref . the feedback signal is applied to the inverting input and the reference is connected to the non ? inverting input of the error amplifier. a resistor divider scales down v bulk to generate the pfc feedback signal. v ref is trimmed during manufacturing to achieve an accuracy of 2.4%. regulation block and low output voltage detection a transconductance error amplifier (ota) with access to the inverting input and output is provided. access to the inverting input is provided by the fb pin and the output is accessible through the control pin. the ota features a typical transconductance gain, g m , of 210 s. the amplifier source and sink currents, i ea(src) and i ea(snk) , are typically 20 a. the output voltage of the pfc stage is typically scaled down by a resistors divider and fed into the fb pin. the pin input bias current is minimized (less than 500 na) to allow the use of a high impedance feedback network. at the same time, the bias current is enough to effectively ground the fb if the pin is open or floating. the output of the error amplifier is brought to the control pin for external loop compensation. the compensation network on the control pin is selected to filter the bulk voltage ripple such that a constant control voltage is maintained across the ac line cycle and provide adequate phase boost. typically a type 2 network is used, to set the
ncp1615 http://onsemi.com 18 regulation bandwidth below about 20 hz and to provide a decent phase boost. the minimum control voltage, v control(min) is typically 0.5 v and it is set by an internal diode drop or v f . maximum control voltage, v control(max) is typically 4.5 v. therefore, the v control swing is 4 v. v control is offset down by a v f and scaled down by a resistor divider before it connects to the ?v ton processing block? and the pwm section as shown in figure 12. the output of the regulation block is a signal (?v regul ? of the block diagram) that varies between 0 and a maximum value corresponding to the maximum on ? time. figure 12. regulation block diagram (left) correspondence between v control and v regul (right) v regul v regul(max) v control in_regulation v dd v f v f + 4 v v uvp1 v sovp v dre 0.5 v staticovp (0.5v bottom clamp is activated) 0.5v bottom clamp 0.5 v i fb(bias) uvp2 softovp error amplifier + ? v ref v dd pfc_ok control off fb + ? v regul 4 v dre comparator soft ? ovp comparator uvp comparator i boost(dre) i control(bo) 3r r regulation detector v fovp fastovp fast ? ovp comparator v dd i boost(startup) stop pfc_ok bo_nok uvp given the low bandwidth of the regulation loop, abrupt variations of the load, may result in excessive over or undershoots. the ncp1615 embeds a ?dynamic response enhancer? circuitry (dre) that limits output voltage undershoots. an internal comparator monitors the fb pin and if its voltage falls below 95.5% of its nominal value, it enables a pull ? up current source, i boost(dre) , to increase the control voltage by charging the compensation network and bring the system into regulation. the total current sourced from the control pin during dre, i control(dre) , is typically 220 a. this effectively appears as a 10x increase in the loop gain. for versions a and b, i boost(dre) is disabled until the pfcok signal goes high. the slow and gradual charge of the control capacitor during power up softens the start ? up sequence effectively achieving a soft ? start. for versions c and d, a reduced current source, i boost(start ? up) (typically 80 a), is enabled to speed up the start ? up sequence and achieve a faster start ? up time. i boost(start ? up) is disabled when faults (i.e. brownout) are detected. voltage overshoots are limited by the soft overvoltage protection (sovp) connected to the fb pin. the circuit reduces the power delivery when the output voltage exceeds 105% of its desired level. the ncp1615 does not abruptly interrupt the switching. instead, the v ton signal that controls the on time is gradually decreased by grounding the v regul signal applied to the v ton processing block as shown in figure 11. doing so, the on time smoothly decays to zero in 3 to 4 cycles. if the output voltage keeps increasing, the fast overvoltage protection (fovp) comparator immediately disables the driver when the output voltage exceeds 107% of its desired level. the undervoltage (uvp) comparator monitors the fb voltage and disables the pfc stage if the bulk voltage falls below 12% of its regulation level. once an undervoltage fault is detected, the pfcok signal goes low to disable the downstream converter and the control capacitor is grounded. the bulk undervoltage comparator (buv) monitors the bulk voltage and disables the controller if the buv voltage falls below the buv threshold. the buv threshold is a ratio of v ref and it is given by k buv/vref , typically 76% of v ref . once a buv fault is detected the controller is disabled and the pfcok signal goes low. the control capacitor is slowly discharged until it falls below the skip level. the discharge delay forces a minimum off time for the downstream converter. once the discharge phase is complete the circuit may attempt to restart if v cc is above v cc(on) . otherwise, it will restart at the next v cc(on) . the buv fault is blanked while the pfcok signal is low (i.e. during start ? up) to allow a correct start ? up sequence.
ncp1615 http://onsemi.com 19 a dedicated comparator monitors the fb voltage to detect the presence of a line overvoltage (lovp) fault. the line overvoltage threshold, v fb(lovp) , is typically 112.5%. a timer, t lovp(blank) , typically 50 s, blanks the line detect signal to prevent false detection during line transients and surge. once a line ovp fault is detected the converter is latched. the input to the error amplifier, the soft-ovp, line ovp, uvp and dre comparators is the fb pin. the table below shows the relationship between the nominal output voltage, v out(nom) , and the dre, soft-ovp, fast-ovp, line ovp and uvp levels. parameter symbol/value nominal output voltage v out(nom) dre threshold v out(nom) *95.5% soft ? ovp v out(nom) *105% uvp v out(nom) *12% fast ? ovp v out(nom) *107% line ? ovp v out(nom) *112.5% current sense and zero current detection the ncp1615 combines the pfc current sense and zero current detectors (zcd) in a single input terminal, cs/zcd. figure 13 shows the circuit schematic of the current sense and zcd detectors. figure 13. pfc current sense and zcd detectors schematic cs/zcd current limit comparator v ocp zcd comparator v zcd(rising)/ v zcd(falling) v dd leb t ovs(leb) detection of excessive current drv ocp overstress zcd drv leb t ocp(leb) drv + ? + ? v dd t off1 i cs/zcd1 i cs/zcd2 current sense the pfc switch current is sensed across a sense resistor, r sense , and the resulting voltage ramp is applied to the cs/zcd pin. the current signal is blanked by a leading edge blanking (leb) circuit. the blanking period eliminates the leading edge spike and high frequency noise during the switch turn ? on event. the leb period, t ocp(leb) , is typically 200 ns. the current limit comparator disables the driver once the current sense signal exceeds the overcurrent threshold, v ocp , typically 0.5 v. pfc zero current detection the cs pin is also designed to receive a signal from an auxiliary winding to detect the inductor demagnetization or for zero current detection (zcd). this winding is commonly known as a zero crossing detector (zcd) winding. this winding provides a scaled version of the inductor voltage. figure 14 shows the zcd winding arrangement. figure 14. zcd winding implementation cs/zcd + pfc output voltage ? + recitied ac line voltage ? + v zcd ? r zcd1 r zcd2 r cs pfc inductor r sense pfc switch drv d zcd the zcd winding voltage, v zcd , is positive while the pfc switch is off and the inductor current decays to zero. v zcd drops to and rings around zero volts once the inductor is demagnetized. the zcd winding voltage is applied through a diode, d zcd , to prevent this signal from distorting the current sense information during the on time. therefore, the overcurrent protection is not impacted by the zcd sensing circuitry. as illustrated in figure 13, an internal zcd comparator monitors the cs/zcd voltage, v cs/zcd . the start of the demagnetization phase is detected (signal zcd is high) once v cs/zcd exceeds the zcd arming threshold, v zcd(rising) , typically 750 mv. this comparator is able to detect zcd pulses with a duration longer than 200 ns. when v cs/zcd drops below the lower or trigger zcd threshold, v zcd(falling) , the end of the demagnetization phase is detected and the driver goes high within 200 ns. when a zcd signal is not detected during start ? up or during the off time, an internal watchdog timer, t off1 , initiates the next drive pulse. the watchdog timer duration is typically 200 s. once the watchdog timer expires the circuit senses the impedance at the cs/zcd pin to detect if the pin is shorted and disable the controller. the cs/zcd external components must be selected to avoid false fault detection. the recommended minimum impedance connected to the cs/zcd pin is 3.9 k . practically, r cs in figure 14 must be higher than 3.9 k . power saving mode versions c and d of the ncp1615 has a low current consumption mode known as power saving mode (psm). the supply current consumption in this mode is below 100 a. psm operation is controlled by an external control signal. this signal is typically generated on the secondary side of the power supply and fed via an optocoupler.
ncp1615 http://onsemi.com 20 the ncp1615 enters psm in the absence of the control signal. the control signal is applied to the pstimer pin. the block diagram is shown in figure 15. power saving mode operating waveforms are shown in figure 16. the ncp1615 controller starts once v cc reaches v cc(on) and no faults are present. the pstimer pin is held at ground until the pfcok signal goes high. this ensures the time to enter psm is always constant. once the pfcok signal goes high, the current source on the pstimer pin, i pstimer1 , is enabled. i pstimer1 is typically 5.9 a. the current source charges the capacitor connected from this pin to ground. once v pstimer reaches v pstimer2 a 2 nd current source, i pstimer2 , is enabled to speed up the charge of c psm . v pstimer2 and i pstimer2 are typically 1 v and 1 ma, respectively. the controller enters psm if the voltage on this exceeds, v ps_in , typically 3.5 v. an external optocoupler or switch needs to pull down on this pin before its voltage reaches v ps_in to prevent entering psm. i pstimer is disabled once the controller enters psm. a resistor between this pin and ground discharges the pstimer capacitor. the controller exits psm once v pstimer drops below v ps_out , typically 0.5 v. at this time the start ? up circuit is enabled to charge v cc up to v cc(on) . once v cc charges to v cc(on) the capacitor on the pstimer pin is discharged with an internal pull down transistor. the transistor is disabled once the pfcok signal goes high. the time to enter psm mode is calculated using equations 3 through 7. the time to exit psm mode is calculated using equation 8. t psm(in) t psm(in1) t psm(in2) (eq. 5) t psm(in1) ? r psm c psm ln 1
v pstimer2 i pstimer1 *r psm (eq. 6) t psm(in2) ? r psm c psm ln 1
v ps_in
v pstimer2 i pstimer2 *r psm (eq. 7) t psm(out) ? r psm c psm ln v ps_out v ps_in (eq. 8) during psm, the start ? up circuit on the hv pin maintains v cc above v cc(off) . the input filter capacitor discharge circuitry continues operation in psm. the supply voltage is maintained in psm by enabling the hv pin start ? up circuit once v cc falls below v cc(ps_on) (typically 11 v) and v hv is at its minimum value as detected by the valley detection circuitry. the start ? up circuit current in psm is increased to i start2 , typically 12 ma, to reduce the time the start ? up circuit is on and thus a lower voltage on the hv pin. the start ? up circuit is disabled once v cc exceeds v cc(ps_on) . a voltage offset is observed on v cc while the start ? up circuit is enabled due to the capacitor esr. this will cause the start ? up circuit to turn off because v cc exceeds v cc(ps_on) . internal circuitry prevents the start ? up circuit from turning on multiple times on the same ac line half ? cycle. the start ? up circuit will turn on the next half ? cycle. eventually, v cc will be regulated several millivolts below v cc(ps_on) . the offset is dependent on the capacitor esr. this architecture enables the start ? up circuit for the exact amount of time needed to regulate v cc . this results in a significant reduction in power dissipation because the average input voltage during which the start ? up circuit is on is greatly reduced. figure 16 shows operating waveforms while in psm. figure 15. ncp1615 power saving mode control block diagram pstimer + ? v pstimer2 v dd v dd v ps_in/ v ps_out + ? initial discharge psm control c psm r psm in psm mode detector i pstimer1 i pstimer2 in psm in psm pfcok power saving
ncp1615 http://onsemi.com 21 figure 16. power saving mode operating waveforms since the ncp1615 maintains the v cc pin at v cc(ps_on) during psm, the current consumption of the downstream converter can have an undesirable impact to power consumption. a simple mechanism to disconnect the supply voltage to the downstream converter during psm is shown in figure 17. figure 17. downstream converter supply removal circuit pfcok vcc vcc enable pfc converter downstream converter bypass/boost diode short circuit and inrush current protection it may be possible to turn on the mosfet while a high current flows through the inductor. examples of this condition include start ? up when large inrush current is present to charge the bulk capacitor . traditionally , a bypass diode is generally placed between the input and output high ? voltage rails to divert this inrush current. if this diode is accidentally shorted or damaged, the mosfet will operate at a minimum on time but the current can be very high causing a significant temperature increase. the ncp1615 operates in a very low duty ratio to reduce the mosfet temperature and protect the system in this ?over stress? condition. this is achieved by disabling the drive signal if the v zcd(rising) threshold is reached during the mosfet conduction time. in this condition, a latch is set and the ?overstress? signal goes high. the driver is then disabled for a period determined by the overstress watchdog timer, t off2 , typically 1 ms. this longer delay leads to a very low duty ? ratio operation to reduce the risk of overheating. this operation also protects the system in the event of a boost diode short.
ncp1615 http://onsemi.com 22 figure 18. current sense and zero current detection blocks v ocp s r q drv ocp overstress zcd signal for valley detection and ccff cs/zcd r sense drv q1 d1 c bulk c in current limit comparator leb t ovs(leb) r cs r zcd1 r zcd2 d zcd v in v out ac in zcd comparator v zcd(rising) / v zcd(falling) overstress watchdog timer (t off2 ) leb t ocp(leb) pfcok signal the pfcok pin provides a dedicated 5 v reference when the pfc stage is in regulation. the pin is internally grounded during the following conditions: ? during start ? up: it remains low until the output voltage achieves regulation and the voltage stabilizes at the right level. ? low output voltage: if the pfc stage output voltage is below the bulk undervoltage (buv_fault) level, this is indicative of a fault. the pfcok signal then provides a means to disable and protect the downstream converter. ? brownout fault is detected (after discharge of control capacitor). ? low supply voltage: v cc falls below v cc(off) . ? feedback undervoltage fault. ? fault condition: a fault detected through the fault pin. ? open fb pin. ? thermal shutdown. ? line voltage removal. the circuit schematic of the pfcok block is shown figure 19. figure 19. pfcok circuit schematic pfc_ok r s q dominant reset latch q pfcok ovlflag off buv_fault line_ovp in_regulation the pfcok circuit monitors the current sourced by the ota. the ota current reaches zero when the output voltage has reached its nominal level. this is represented in the block diagram by the ?in_regulation? signal. the pfcok signal goes high when the current reaches zero or falls below zero. the start ? up phase is then complete and the pfcok signal goes high until a fault is detected. another signal considered before setting the pfcok signal is the buv. the pfcok signal will remain low until the bulk voltage is above the undervoltage threshold. the pfcok signal will go low if the bulk voltage drops below its undervoltage threshold. brownout detection the hv pin provides access to the brownout and line voltage detectors. it also provides access to the input filter capacitor discharge circuit. the brownout detector detects main interruptions and the line voltage detector determines the presence of either 110 v or 220 v ac mains. depending on the detected input voltage range device parameters are internally adjusted to optimize the system performance. line and neutral are diode ?ored? before connecting to the hv pin as shown in figure 20. the diodes prevent the pin voltage from going below ground. a low value resistor in series with the diodes can be used for protection. a low value resistor is needed to reduce the voltage offset while sensing the line voltage. figure 20. high ? voltage input connection emi ac in hv controller filter the controller is enabled once v hv is above the brownout threshold, v bo(start) , typically 111 v, and v cc reaches v cc(on) . figure 21 shows typical power up waveforms.
ncp1615 http://onsemi.com 23 figure 21. start ? up timing diagram a timer is enabled once v hv drops below its disable threshold, v bo(stop) , typically 99 v. the controller is disabled if v hv doesn?t exceed v bo(stop) before the brownout timer expires, t bo , typically 54 ms. the timer is set long enough to ignore a single cycle dropout. the timer ramp starts charging once v hv drops below v bo(stop) . figure 22 shows brownout detector waveforms during line dropout.
ncp1615 http://onsemi.com 24 figure 22. brownout operation during line dropout line range detector the input voltage range is detected based on the peak voltage measured at the hv pin. the line range detection circuit allows more optimal loop gain control for universal (wide input mains) applications. discrete values are selected for the pfc stage gain (feedforward) depending on the input voltage range. the controller compares v hv to the high line select threshold, v lineselect(hl) , typically 250 v. once v hv exceeds v lineselect(hl) , the pfc stage operates in ?high line? (europe/asia) or ?220 vac? mode. in high line mode the loop gain is divided by four (the internal pwm ramp slope is four times steeper). the default power ? up mode of the controller is low line. the controller switches to ?high line? mode if v hv exceed the high line select threshold for longer than the low to high line timer, t delay(line) , typically 300 s as long as it was not previously in high line mode. if the controller has switched to ?low line? mode, it is prevented from switching back to ?high line? mode until the valley detection circuit detects 8 valleys, even if t delay(line) has expired. the timer and logic is included to prevent unwanted noise from toggling the operating line level. in ?high line? mode the high to low line timer, t line , (typically 54 ms) is enabled once v hv falls below v lineselect(ll) , typically 236 v. it is reset if v hv exceeds v lineselect(ll) . the controller switches back to ?low line? mode if the high to low line timer expires. figures 23 and 24 show operating waveforms of the line detector circuit.
ncp1615 http://onsemi.com 25 figure 23. line detector timing waveforms figure 24. valley counter operation
ncp1615 http://onsemi.com 26 output drive section the ncp1615 incorporates a large mosfet driver. it is a totem pole optimized to minimize the cross conduction current during high frequency operation. it has a high drive current capability ( ? 500/+800 ma) allowing the controller to effectively drive high gate charge power mosfet. the device maximum supply voltage, v cc(max) , is 30 v. typical high voltage mosfets have a maximum gate voltage rating of 20 v. the driver incorporates an active voltage clamp to limit the gate voltage on the external mosfets. the voltage clamp, v drv(high) , is typically 12 v with a maximum limit of 14 v. the gate driver is kept in a sinking mode whenever the controller is disabled. this occurs when the undervoltage lockout is active or more generally whenever the controller detects a fault and enters off mode (i.e., when the ?stdwn? signal of the block diagram is high). off mode the controller is disabled and in a low current mode if any of the following faults are detected: ? low supply input voltage. an undervoltage (or uvlo) fault is detected if v cc falls below v cc(off) . ? thermal shutdown is activated due to high die temperature. ? a brownout fault is detected. ? the controller enters skip mode (see block diagram) ? a bulk undervoltage fault is detected. ? the controller enters latch mode. generally speaking, the circuit turns off when the conditions are not proper for desired operation. in this mode, the controller stops operation and most of the internal circuitry is disabled to reduce power consumption. below is description of the ic operation in off mode: ? the driver is disabled. ? the controller maintains v cc between v cc(on) and v cc(off) . ? the following blocks or features remain active: ? brownout detector. ? thermal shutdown. ? the undervoltage protection (?uvp?) detector. ? the overvoltage latch input remains active ? v control is grounded to ensure a controlled start ? up sequence once the fault is removed. ? the pfcok pin is internally grounded. ? the output of the ?v ton processing block? is grounded.
ncp1615 http://onsemi.com 27 system failure detection when manufacturing a power supply, elements can be accidentally shorted or improperly soldered. such failures can also occur as the system ages due to component fatigue, excessive stress, soldering faults, or external interactions. in particular, a pin can be grounded, left open, or shorted to an adjacent pin. such open/short situations require a safe failure without smoke, fire, or loud noises. the ncp1615 integrates functions that ease meeting this requirement. among them are: ? gnd connection fault. if the gnd pin is properly connected, the supply current drawn from the positive terminal of the vcc capacitor, flows out of the gnd pin and returns to the negative terminal of the vcc capacitor. if the gnd pin is disconnected, the internal esd protection diodes provides a return path. an open or floating gnd pin is detected if current flows in the cs/zcd esd diode. if current flow is detected for 200 s, a fault is acknowledged and the controller stops operating. ? open cs/zcd pin: a pull-up current source, i cs/zcd(bias1) , on the cs/zcd pin allows detection of an open cs/zcd pin. i cs/zcd1 , is typically 1 a. if the pin is open, the voltage on the pin will increase to the supply rail. this condition is detected and the controller is disabled. ? grounded cs/zcd pin: if the cs/zcd pin is grounded, the circuit cannot detect a zcd transition, activating the watchdog timer (typically 200 s). once the watchdog timer expires, a pull-up current source, i cs/zcd2 , sources 250 a to pull-up the cs/zcd pin. the driver is inhibited until the cs/zcd pin voltage exceeds the zcd arming threshold, v zcd(rising) , typically 0.75 v. therefore, if the pin is grounded, the voltage on the pin will not exceed v zcd(rising) and drive pulses will be inhibited. the external impedance should be above 3.9 k to ensure correct operation. ? boost or bypass diode short. the ncp1615 addresses the short situations of the boost and bypass diodes (a bypass diode is generally placed between the input and output high-voltage rails to divert this inrush current). practically, the overstress protection is implemented to detect such conditions and forces a low duty ratio operation until the fault is removed. fault input the ncp1615 includes a dedicated fault input accessible via the fault pin. the controller can be latched by pulling up the pin above the upper fault threshold, v fault(ovp) , typically 3.0 v. the controller is disabled if the fault pin voltage, v fault , is pulled below the lower fault threshold, v fault(otp_in) , typically 0.4 v. the lower threshold is normally used for detecting an overtemperature fault. the controller operates normally while the fault pin voltage is maintained within the upper and lower fault thresholds. figure 25 shows the architecture of the fault input. the lower fault threshold is intended to be used to detect an overtemperature fault using an ntc thermistor. a pull up current source i fault(otp) , (typically 45.5 a) generates a voltage drop across the thermistor. the resistance of the ntc thermistor decreases at higher temperatures resulting in a lower voltage across the thermistor. the controller detects a fault once the thermistor voltage drops below v fault(otp_in) . versions a and c latch-off the controller after an overtemperature fault is detected. in versions b and d the controller is re-enabled once the fault is removed such that v fault increases above v fault(otp_out) and v cc reaches v cc(on) . figure 26 shows typical waveforms related to the latch version where ? as figure 27 shows waveforms of the auto-recovery version. an active clamp prevents the fault pin voltage from reaching the upper latch threshold if the pin is open. to reach the upper threshold, the external pull-up current has to be higher than the pull-down capability of the clamp (set by r fault(clamp) at v fault(clamp) ). the upper fault threshold is intended to be used for an overvoltage fault using a zener diode and a resistor in series from the auxiliary winding voltage, v aux . the controller is latched once v fault .exceeds v fault(ovp) . the fault input signal is filtered to prevent noise from triggering the fault detectors. upper and lower fault detector blanking delays, t delay(ovp) and t delay(otp) are both typically 30 s. a fault is detected if the fault condition is asserted for a period longer than the blanking delay. the controller bias current is reduced during power up by disabling most of the circuit blocks including i fault(otp) . this current source is enabled once v cc reaches v cc(on) . a bypass capacitor is usually connected between the fault and gnd pins and it will take some time for v fault to reach its steady state value once i fault(otp) is enabled. to prevent false detection of an otp fault during power up, a dedicated timer, t blank(otp) , blanks the otp signal during power up. the t blank(otp) , duration is typically 5 ms. in versions b and d, i fault(otp) remains enabled while the lower fault is present independent of v cc in order to provide temperature hysteresis. i fault(otp) is disabled once the fault is removed. the controller can detect an upper fault (i.e. overvoltage) once v cc exceeds v cc(reset) . once the controller is latched, it is reset if a brownout condition is detected or if v cc is cycled down to its reset level, v cc(reset) . in the typical application these conditions occur only if the ac voltage is removed from the system. the internal latch also resets once the controller enters power saving mode. prior to reaching v cc(reset) v fault(clamp) is set at 0 v.
ncp1615 http://onsemi.com 28 figure 25. fault detection schematic figure 26. latch ? off function timing diagram time internal latch signal time time qdrv latch signal high during pre ? start phase noise spike blanked switching allowed (no latch event) latch ? off v cc(off) v cc(on) v cc start ? up initiated by v cc(on)
ncp1615 http://onsemi.com 29 figure 27. otp auto ? recovery timing diagram standby operation a signal proportional to the downstream converter output power is applied to the stdby pin to enable standby mode operation. a stdby voltage below the standby threshold, v standby , typically 300 mv, forces the controller into a controlled burst mode, or standby mode. in standby mode, the driver is disabled until the bulk voltage falls below the bulk restart level. at which point, the driver is re ? enabled. the bulk restart level determines the minimum bulk voltage in standby mode. as long as the stby pin voltage is below the standby threshold, the controller will operate in controlled burst mode. the controller is not allowed to enter standby mode while the pfcok signal is low. a dedicated timer, t blank(stdby) , blanks the standby signal for 1 ms (typically) right after the pfcok signal transitions high. this ensures the signal proportional to the downstream converter output power has enough time to build up and prevent disabling the pfc while powering up the downstream converter. the standby circuit block is shown in figure 28. figure 28. standby circuit block t blank(stdby) in_regulation v standby stdby q drv disable s r pfc_ok 0.98*v ref restart i restart v uvp3 uvp3 adjustable bulk voltage hysteresis the bulk restart threshold allows the user to enable the bulk level at which the controller exits standby mode. the restart threshold is set at 2% below the internal reference, v ref . the ratio between v ref and the restart level is given by k restart . the user can set a restart level of 2% below the regulation level without using additional components as shown in figure 29. if a different restart level is desired, a resistor network can be used as shown in figure 30. figure 29. minimum restart level configuration
ncp1615 http://onsemi.com 30 figure 30. restart level adjustment i fb(snk) i restart(bias) a pull-down current source, i restart(bias) , pulls the restart pin down to ground if it is left open. this triggers the open pin protection and disables the controller. line removal safety agency standards require the input filter capacitors to be discharged once the ac line voltage is removed. a resistor network is the most common method to meet this requirement. unfortunately, the resistor network consumes power across all operating modes and it is a major contributor of input power losses during light ? load and no ? load conditions. the ncp1615 eliminates the need of external discharge resistors by integrating active input filter capacitor discharge circuitry. a novel approach is used to reconfigure the high voltage start ? up circuit to discharge the input filter capacitors upon removal of the ac line voltage. the line removal detection circuitry is always active to ensure safety compliance. the line removal is detected by digitally sampling the voltage present at the hv pin, and monitoring the slope. a timer, t line(removal) (typically 100 ms), is used to detect when the slope of the input signal is negative or below the resolution level. the timer is reset any time a positive slope is detected. once the timer expires, a line removal condition is acknowledged initiating an x2 capacitor discharge. once the controller detects the absence of the ac line voltage, the controller is disabled and the pfcok signal transitions low. a second timer, t line(discharge) (typically 32 ms), is used for the time limiting of the discharge phase to protect the device against overheating. once the discharge phase is complete, t line(discharge) is reused while the device checks to see if the line voltage is reapplied. the discharging process is cyclic and continues until the ac line is detected again or the voltage across the x2 capacitor is lower than v hv(discharge) (30 v maximum). this feature allows the device to discharge large x2 capacitors in the input line filter to a safe level. it is important to note that the hv pin cannot be connected to any dc voltage due to this feature, i.e. directly to bulk capacitor. the diodes connecting the ac line to the hv pin should be placed after the system fuse. a resistor in series with the diodes is recommended to limit the current during transient events. a low value resistor (< 3 k ) should be used to reduce the voltage drop and accurately measure the input voltage when the start ? up circuit is enabled.
ncp1615 http://onsemi.com 31 figure 31. line removal timing v bo(start) v bo(stop)
ncp1615 http://onsemi.com 32 figure 32. line removal timing with ac reapplied v bo(start) v bo(stop)
ncp1615 http://onsemi.com 33 v cc discharge if the downstream converter is latched due to a fault, it will require the supply voltage to be removed to reset the controller. depending on the supply capacitor and current consumption, this may take a significant amount of time after the line voltage is removed. the ncp1615 uses the voltage at the hv pin to detect a line removal and discharge the v cc capacitor, effectively resetting the downstream converter. immediately following the x2 discharge phase, v cc is discharged by a current sink, i cc(discharge) , typically 23 ma. the current sink is disabled and the device is allowed to restart once v cc to falls down to v cc(discharge) (5 v maximum). this operation is shown in figure 31. if the ac line is reapplied during the x2 discharge phase, the device will immediately enter the v cc discharge phase as shown in figure 32. the device will not restart until the v cc discharge phase is completed and v cc charges to v cc(on) . feedback disconnect the pfc output voltage is typically sensed using a resistor divider comprised of r3 and r4 as shown in figure 33. the resistor divider consumes power when the pfc stage is disabled. versions c and d of the ncp1615 integrate a 700 v switch, pfc fb switch, between the fbhv and fb pins. the pfc fb switch connects in series between r3 and r4 to disconnect the resistors and reduce input power when the pfc stage is in psm or latched mode. figure 33. pfc fb switch the maximum on resistance of the pfc fb switch, r pfbswitch(on) , is 10 k . because the pfc fb switch is in series with r3 and r3?s value is several orders of magnitudes larger, the switch introduces minimal error on the regulation level. the off state leakage current of the pfc fb switch, i pfbswitch(off) , is less than 3 a. temperature shutdown an internal thermal shutdown circuit monitors the junction temperature of the ic. the controller is disabled if the junction temperature exceeds the thermal shutdown threshold, t shdn , typically 150 c. a continuous v cc hiccup is initiated after a thermal shutdown fault is detected. the controller restarts at the next v cc(on) once the ic temperature drops below below t shdn by the thermal shutdown hysteresis, t shdn(hys) , typically 50 c. the thermal shutdown fault is also cleared if v cc drops below v cc(reset) , or if a brownout/line removal fault is detected. a new power up sequences commences at the next v cc(on) once all the faults are removed.
ncp1615 http://onsemi.com 34 typical characteristics figure 34. v cc(on) (version a/b) vs. temperature figure 35. v cc(on) (version c/d) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 10.395 10.400 10.405 10.410 10.415 10.420 10.425 10.430 100 80 60 40 20 0 ? 20 ? 40 16.79 16.80 16.81 16.82 16.83 16.84 16.85 16.86 v cc(on) (v) v cc(on) (v) 120 120 figure 36. v cc(off) vs. temperature figure 37. v cc(hys) (version a/b) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 8.945 8.950 8.955 8.960 8.965 8.970 8.975 100 80 60 40 20 0 ? 20 ? 40 1.4755 1.4760 1.4765 1.4770 1.4775 1.4780 1.4785 1.4790 figure 38. v cc(hys) (version c/d) vs. temperature figure 39. v cc(reset) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 7.845 7.850 7.855 7.860 7.865 7.875 7.880 7.885 100 80 60 40 20 0 ? 20 ? 40 7.66 7.68 7.70 7.72 7.74 7.76 7.78 7.80 v cc(off) (v) v cc(hys) (v) v cc(hys) (v) v cc(reset) (v) 120 120 120 120 7.870
ncp1615 http://onsemi.com 35 typical characteristics figure 40. v cc(inhibit) vs. temperature figure 41. t startup vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 0 0.1 0.3 0.4 0.6 0.7 0.9 1.0 100 80 60 40 20 0 ? 20 ? 40 0 0.2 0.4 0.8 1.0 1.4 1.6 1.8 v cc(inhibit) (v) t startup (ms) 120 120 0.2 0.5 0.8 0.6 1.2 figure 42. i start1 (version c/d) vs. temperature figure 43. i start2 (version c/d) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 0.510 0.515 0.520 0.525 0.530 0.535 100 80 60 40 20 0 ? 20 ? 40 11.6 11.7 11.8 11.9 12.0 12.1 12.2 12.3 figure 44. i hv(off1) vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 20.35 20.40 20.50 20.55 20.65 20.70 20.80 20.85 i start1 (ma) i start2 (ma) i hv(off1) ( a) 120 120 120 20.45 20.60 20.75 figure 45. i cc1 vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 0.042 0.043 0.044 0.045 0.047 0.048 0.050 0.051 i cc1 (ma) 120 0.046 0.049
ncp1615 http://onsemi.com 36 typical characteristics figure 46. i cc2 vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 0.61 0.62 0.63 0.64 0.65 0.66 0.67 0.68 figure 47. i cc2b (version a/b) vs. temperature figure 48. i cc3 vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 0.58 0.59 0.60 0.61 0.62 0.63 0.64 0.65 100 80 60 40 20 0 ? 20 ? 40 0.82 0.83 0.85 0.86 0.88 0.89 0.91 0.92 figure 49. i cc4 vs. temperature figure 50. i cc5 vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 2.45 2.46 2.48 2.50 2.51 2.53 2.54 2.56 100 80 60 40 20 0 ? 20 ? 40 2.85 2.90 2.95 3.00 3.05 3.10 i cc2 (ma) i cc2b (ma) i cc3 (ma) i cc4 (ma) i cc5 (ma) 120 120 120 120 120 0.84 0.87 0.90 2.47 2.49 2.52 2.55 figure 51. t line(removal) vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 0 20 40 60 80 100 120 140 t line(removal) (ms) 120
ncp1615 http://onsemi.com 37 typical characteristics figure 52. t line(discharge) vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 0 5 15 20 25 30 40 45 t line(discharge) (ms) 120 10 35 figure 53. v bo(start) (version a/b/c/d) vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 109.0 109.5 110.0 110.5 111.0 111.5 112.0 v bo(start) (v) 120 figure 54. v bo(start) (version c2) vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 93.2 93.4 93.8 94.0 94.2 94.6 95.0 95.2 figure 55. v bo(stop) (version a/b/c/d) vs. temperature figure 56. v bo(stop) (version c2) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 98.6 98.8 99.2 99.4 99.8 100.2 100.4 100.8 100 80 60 40 20 0 ? 20 ? 40 85.2 85.4 85.6 86.0 86.2 86.4 86.8 87.0 figure 57. v bo(hys) (version a/b/c/d) vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 10.65 10.70 10.75 10.80 10.85 10.90 v bo(start) (v) v bo(stop) (v) v bo(stop) (v) v bo(hys) (v) 120 120 120 120 93.6 94.4 94.8 99.0 99.6 100.0 100.6 85.8 86.6
ncp1615 http://onsemi.com 38 typical characteristics figure 58. v bo(hys) (version c2) vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 7.94 7.96 7.98 8.00 8.04 8.06 8.08 8.10 v bo(hys) (v) 120 8.02 figure 59. v lineselect(hl) vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 245.0 246.0 245.5 246.5 247.0 249.0 249.5 250.5 v lineselect(hl) (v) 120 247.5 248.0 248.5 250.0 figure 60. v lineselect(ll) vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 232.0 232.5 233.0 234.0 234.5 235.5 236.5 237.0 v lineselect(ll) (v) 120 233.5 235.0 236.0 figure 61. v lineselect(hys) vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 12.8 12.9 13.1 13.2 13.3 13.4 13.6 13.7 v lineselect(hys) (v) 120 13.0 13.5 figure 62. i hvfb(off) vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 0 0.05 0.10 0.15 0.20 0.25 0.30 figure 63. r fbswitch(on) vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 0 0.5 1.0 1.5 2.0 2.5 i fbhv(off) ( a) r fbswitch(on) (k ) 120 120
ncp1615 http://onsemi.com 39 typical characteristics figure 64. v ref vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 2.488 2.490 2.492 2.496 2.498 2.500 2.504 2.506 v ref (v) 120 2.494 2.502 figure 65. g m vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 214.4 214.6 214.8 215.0 215.2 215.4 215.6 g m ( s) 120 figure 66. v dre vs. temperature figure 67. v dre(hys) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 2.378 2.380 2.382 2.384 2.386 2.388 2.390 2.394 100 80 60 40 20 0 ? 20 ? 40 0 1 2 3 4 5 6 v dre (v) v dre(hys) (mv) 120 120 2.392 figure 68. t on(ll) vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 23.5 23.6 23.7 23.8 23.9 24.0 24.1 24.2 t on(ll) ( s) 120 figure 69. t on(hl) vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 5.90 5.92 5.94 5.96 5.98 6.00 6.02 6.04 t on(hl) ( s) 120
ncp1615 http://onsemi.com 40 typical characteristics figure 70. v ilim vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 0.5045 0.5050 0.5055 0.5060 0.5065 0.5070 0.5075 0.5080 figure 71. t ocp(leb) vs. temperature figure 72. t ocp(delay) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 160 162 164 168 170 174 176 178 100 80 60 40 20 0 ? 20 ? 40 0 20 40 60 80 100 120 v ilim (v) t ocp(leb) (ns) t ocp(delay) (ns) 120 120 120 166 172 figure 73. t ovs(leb) vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 71 72 74 75 77 78 79 81 t ovs(leb) (ns) 120 73 76 80 figure 74. t ovs(delay) vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 0 10 20 30 40 60 70 80 t ovs(delay) (ns) 120 50 figure 75. t zcd vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 0 20 40 60 100 120 140 160 t zcd (ns) 120 80
ncp1615 http://onsemi.com 41 typical characteristics figure 76. t dt2 vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 6.18 6.19 6.21 6.22 6.24 6.26 6.27 6.29 figure 77. t dt3 vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 12.52 12.54 12.56 12.58 12.60 12.62 12.64 t dt2 ( s) t dt3 ( s) 120 120 6.20 6.23 6.25 6.28 figure 78. t drv(rise) vs. temperature figure 79. t drv(fall) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 0 5 10 15 20 25 35 40 100 80 60 40 20 0 ? 20 ? 40 0 5 10 15 20 30 35 40 figure 80. v drv(high2) vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 11.4 11.6 11.8 12.0 12.2 12.4 12.6 t drv(rise) (ns) t drv(fall) (ns) v drv(high2) (v) 120 120 120 25 30 figure 81. i fb(snk1) vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 240 245 255 260 265 275 285 290 i fb(snk1) (na) 120 250 270 280
ncp1615 http://onsemi.com 42 typical characteristics figure 82. i fb(snk2) vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 230 235 245 255 260 270 275 285 i fb(snk2) (na) 120 240 250 265 280 figure 83. i fovp/uvp(bias1) vs. temperature figure 84. i fovp/uvp(bias2) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 232 234 236 238 240 242 244 246 100 80 60 40 20 0 ? 20 ? 40 222 224 226 228 232 234 238 240 i fovp/uvp(bias1) (na) i fovp/uvp(bias2) (na) 120 120 230 236 figure 85. i restart(bias) vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 234 236 238 240 244 246 250 252 i restart(bias) (na) 120 242 248 figure 86. i fault(otp) vs. temperature t j , junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 45.5 45.6 45.7 45.8 45.9 46.0 46.1 i fault(otp) ( a) 120
ncp1615 http://onsemi.com 43 package dimensions soic ? 14 nb, less pin 13 case 751an ? 01 issue a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of at maximum material condition. 4. dimensions d and e do not include mold protrusions. 5. maximum mold protrusion 0.15 per side. h 14 8 7 1 m 0.25 b m c h x 45 seating plane a1 a m dim min max millimeters d 8.55 8.75 e 3.80 4.00 a 1.35 1.75 b 0.35 0.49 l 0.40 1.25 e 1.27 bsc a3 0.19 0.25 a1 0.10 0.25 m 0 7 h 5.80 6.20 h 0.25 0.50 6.50 13x 0.58 13x 1.18 1.27 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. s a m 0.25 b s c b 13x b a e d e detail a l a3 detail a
ncp1615 http://onsemi.com 44 package dimensions soic ? 16 nb, less pin 15 case 752ac ? 01 issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. 4. dimensions d and e do not include mold protrusions. 5. maximum mold protrusion 0.15 per side. 18 16 9 seating plane l m h x 45 e 15x h e d m 0.25 b m a1 a dim min max millimeters d 9.80 10.00 e 3.80 4.00 a 1.35 1.75 b 0.35 0.49 l 0.40 1.25 e 1.27 bsc c 0.19 0.25 a1 0.10 0.25 m 0 7 h 5.80 6.20 h 0.25 0.50 6.40 15x 0.58 15x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint* 16 89 m 0.25 a s b 15x t b s a b c c *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp1615/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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